module RegFile (
    /* verilator lint_off UNOPTFLAT */
    input wire clk,
    input wire rst,
    input wire rf_we,//写使�?
    input wire [4:0] raddr1,
    input wire [4:0] raddr2,//读地�?
    input wire [4:0] waddr,//写地�?
    input wire [31:0] ALU_C,
    input wire [31:0] SEXT_ext,
    input wire [31:0] DRAM_rd,
    input wire [31:0] NPC_pc4,
    input wire [1:0] rf_wsel,
    
    output reg [31:0] wdata,//为了Trace专门做的输出回到CPU�?
    output wire [31:0] rdata1,
    output wire [31:0] rdata2  //读数�?
    /* verilator lint_off UNOPTFLAT */
);

//写回进来之前的多路�?�择
always @(*) begin
    case (rf_wsel)
        2'b00: wdata = ALU_C;
        2'b01: wdata = SEXT_ext;
        2'b10: wdata = DRAM_rd;
        2'b11: wdata = NPC_pc4;
        default: wdata = wdata;
    endcase
end
//32个�?�用寄存器，其中0号寄存器恒为0
reg[31:0] rf[31:0];
// integer j;
// initial begin
//         for (j = 0; j < 32; j = j + 1) begin
//             rf[j] = 32'h0;  // 使用 32 位十六进制数 0 初始化每个元素
//         end
//     end

//异步�?
assign rdata1 = rf[raddr1];
assign rdata2 = rf[raddr2];

integer i;

//同步�?
always @(posedge clk or posedge rst) begin
    if(rst)begin
        for(i = 0;i<32;i=i+1)rf[i]<=0;
    end
    else if(rf_we && (waddr !=5'b0))begin
        rf[waddr] <= wdata;
    end
end

    
endmodule